As one of the most important high speed parallel interface, LPDDR5 is made up with 16 DQs per DRAM die. To achieve higher performance and lower power than previous generation, LPDDR5 interface is running up to 6400Mbps, with an IO power supply of 0.5V. The single ended structure will expose LPDDR5 to more severe challenges of ISI, crosstalk, and SSN noises than before that will downgrade the IO performance. In this paper, SSN noise is deep dived, and the design space is evaluated with proper on die decoupling strategy, and data encoding.