Technology Lookup Table based Default Timing Assertions for Hierarchical Timing Closure
- Resource Type
- Conference
- Authors
- Ledalla, Ravi; Sinha, Debjit; Bhanji, Adil; Li, Chaobo; Schaeffer, Gregory; Gupta, Hemlata; Basile, Jennifer
- Source
- 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE) Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021. :1558-1563 Feb, 2021
- Subject
- Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Robotics and Control Systems
Integrated circuits
Wires
Tools
Logic gates
Timing
Optimization
Timing analysis
assertions
hierarchical timing
- Language
- ISSN
- 1558-1101
This paper presents an approach to dynamically generating representative external driving cell and external wire parasitic assertions for the ports of sub-blocks of a hierarchical design. The assertions are based on a technology lookup table and use attributes of the port and the hierarchical wire connected to the port as keys. A concept of reverse timing calculation at the input of the driving cell is described that facilitates the approach to drive efficient timing optimization of boundary paths of design sub-blocks. Experimental results in an industrial timing environment demonstrate significantly improved timing optimization accuracy when compared to prior work.