This paper presents hardware implementations of two principle polar decoding algorithms: Successive Cancellation Decoding (SCD) and Successive Cancellation List Decoding (SCL). The proposed designs are compliant with 3GPP specifications in terms of block length and frozen-set mapping. Moreover, this generic architecture allows block length $N$ and rate $R$ to be configured on-the-fly. The implementations significantly improved decoding throughput with hardware optimization, especially with the SCD, thanks to parallel-block decoding technique. Additionally, the SCL with a list size $L\geq 8$ considerably outperforms the Bit-Error-Rate (BER), as well as the Frame-Error-Rate (FER) curve compared to SCD. The paper provides a comparison of the two algorithms, especially the trade-off between performance and complexity. The results of implementations and testing are carried out on FPGA platform and compared with State-Of-The-Art (SOTA).