A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator
- Resource Type
- Conference
- Authors
- Fan, Qingjun; Zhang, Runxi; Bikkina, Phaneendra; Mikkola, Esko; Chen, Jinghong
- Source
- ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) Solid State Circuits Conference (ESSCIRC), ESSCIRC 2019 - IEEE 45th European. :193-196 Sep, 2019
- Subject
- Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
General Topics for Engineers
Photonics and Electrooptics
Power, Energy and Industry Applications
Clocks
Calibration
Latches
Delays
Inverters
MOS devices
- Language
- ISSN
- 2643-1319
This paper presents a 500 MS/s 10-bit single-channel SAR ADC with a reconfigurable double-rate comparator for enhanced operation speed. The proposed double-rate comparator effectively eliminates the delay caused by comparator reset from the critical path while consuming less power and reducing the clock frequency by half. A test chip is fabricated in a 28 nm FDSOI technology. Clocked at 500 MS/s, the proposed ADC achieves a SNDR of 52.7 dB and a SFDR of 62.49 dB at Nyquist with a power consumption of 1.18 mW, showing a Walden FOM of 6.7 fJ/conv.-step.