A hybrid embedded compression codec engine for ultra HD video application
- Resource Type
- Conference
- Authors
- Park, Seongmo; Byun, Kyungjin; Eum, Nak-woong
- Source
- 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) Very Large Scale Integration (VLSI-SoC), 2015 IFIP/IEEE International Conference on. :292-296 Oct, 2015
- Subject
- Components, Circuits, Devices and Systems
Computing and Processing
Algorithm design and analysis
Encoding
Image coding
Computer architecture
Hardware
Prediction algorithms
Bandwidth
lossy compression
lossless compression
embedded compression
video coding
- Language
- ISSN
- 2324-8432
2324-8440
We proposed an efficient VLSI hardware architecture of the High Efficiency Video Coding (HEVC) using a hybrid embedded compression algorithm for reducing the frame memory bandwidth. This architecture was designed to reduce the memory bandwidth using an adaptive prediction lossy/lossless algorithm. We saved about 50% of the memory access cycles for the reference data compared to a previous algorithm. The PSNR degradation of 0.12 dB on average was proposed algorithm at the compression ratio of 50%. The architecture was implemented in Verilog HDL and synthesized using a Synopsys Design Compiler with a 65nm cell library; the gate count was about 25,000 gates.