Development and Use of Small Addressable Arrays for Process Window Monitoring in 65nm Manufacturing
- Resource Type
- Conference
- Authors
- Karthikeyan, Muthu; Gasasira, Arthur; Fox, Stephen; Yeric, Greg; Hall, Michael; Garcia, John; Mitchell, Barry; Wolf, Eric
- Source
- 2007 IEEE International Conference on Microelectronic Test Structures Microelectronic Test Structures, 2007. ICMTS '07. IEEE International Conference on. :135-139 Mar, 2007
- Subject
- Components, Circuits, Devices and Systems
Monitoring
Manufacturing processes
Circuit testing
System testing
USA Councils
Probes
Semiconductor device manufacture
Phased arrays
Read only memory
Microelectronics
Process monitoring
Semiconductor defects
Yield optimization
- Language
- ISSN
- 1071-9032
2158-1029
In this paper we report on the development and use of two scribe-line compatible addressable array test structures in 65nm technology for routine process window monitoring. One array was dedicated for front-end of line test structures, while a second consists exclusively of back-end test structures. Fast testing allows large-scale sampling of wafer lots in a manufacturing environment. Customized software is used to automate data analysis and calculate figures of merit that enable process and equipment performance to be tracked by process module. Examples of successful application of these arrays in identifying and addressing systematic yield detractors are provided.