A variety of computing platforms like Field Pro-grammable Gate Array (FPGA), Graphics Processing Unit (GPU) and multicore Central Processing Unit (CPU) in data centers are suitable for the acceleration of data-intensive workloads. FPGA platforms in data centers are significantly gaining popularity for high-performance computations due to their high speed, re-configurable nature and cost-effectiveness. Heterogeneous, highly parallel computational architectures in data centers and high-speed communication technologies like $5\mathrm{G}$ are becoming in-creasingly suitable for real-time applications. However, flexibility, cost-effectiveness, high computational capabilities and energy efficiency remain challenging issues in FPGA based data centers. This paper introduces a power-aware scheduling methodology to accommodate execution of periodic hardware tasks within the available FPGAs of a data center at their potentially maximum speed. The proposed methodology guarantees the execution of available tasks using the maximum number of parallel compu-tation units (CUs) possible to implement in the FPGAs with minimum power consumption. The proposed scheduling method-ology is implemented in a data center with multiple Alveo- U50 Xilinx-AMD FPGAs and Vitis 2023 tool. The evidence from the implementation shows the proposed scheduling methodology is efficient compared to existing solutions.