A Highly Robust and Low-Power Flip-Flop Cell With Complete Double-Node-Upset Tolerance for Aerospace Applications
- Resource Type
- Periodical
- Authors
- Yan, A.; He, Y.; Niu, X.; Cui, J.; Ni, T.; Huang, Z.; Girard, P.; Wen, X.
- Source
- IEEE Design & Test IEEE Des. Test Design & Test, IEEE. 40(4):34-41 Aug, 2023
- Subject
- Computing and Processing
Components, Circuits, Devices and Systems
Latches
Flip-flops
Delays
Transistors
Microelectronics
Power dissipation
Switches
Low power electronics
Radiation protection
circuit hardening
flip-flop reliability
soft error tolerance
low power
- Language
- ISSN
- 2168-2356
2168-2364
This article proposes a robust and low power flip-flop cell with complete double-node-upset (DNU) tolerance for aerospace applications. The proposed cell is constructed from a master latch and a slave latch. The master latch comprises two C-elements as well as one clock-controlled C-element; the slave latch is similar to the master but has an extra keeper to avoid high-impedance state of the output-level C-element. The proposed cell can provide complete DNU-tolerance while reducing power dissipation by 65x0025; on average when compared with existing radiation-hardened flip-flop cells.