Gallium oxide (Ga$_{2}$O$_{3}$) is attractive as a material for power electronics but its low thermal conductivity has risen concerns about thermal management problems. This article provides a direct evaluation of different assembly strategies for Ga$_{2}$O$_{3}$ Schottky diodes. 600 μm thick (current standard) and novel 200 μm thin large-area $\beta$-Ga$_{2}$O$_{3}$ diodes are assembled on ceramic substrates in cathode-side cooled and junction-side cooled (JSC) configuration, and compared to a commercial SiC reference diode of similar size that was assembled in the same way, which enables a fair comparison. Thermal imaging and measurements of the thermal structure functions reveal the different contributions of die and package to the total thermal resistance. The lowest junction temperature, close to that of the SiC counterpart, is achieved with JSC. By combining the measurements with thermal simulations, it is shown that an optimization of the die attach thickness or the use of underfill materials in JSC configuration could further lower the average junction temperature and decrease local temperature peaks significantly. The influence of the assembly method, substrate thickness, and on-resistance on the power and current rating of the Ga$_{2}$O$_{3}$ diodes is discussed for applications where conduction losses dominate.