This paper presents noise reduction and modified asynchronous logic regulation techniques used in successive approximation register (SAR) analog-to-digital converter (ADC). With a transconductance enhanced structure, noise reduction is provided in the dynamic comparator. The input referred noise of the proposed comparator is about 165 μ V rms at 60∘C (typical corner). An enhanced-positive-feedback loop is introduced to reduce the regeneration delay of the comparator. In addition, a modified asynchronous logic regulation technique is exhibited, a clock with adaptable delay is driving the comparator in approximation phase. Consequently, the settling accuracy of DAC (Digital-to-Analog Converter) is enough and the conversion speed of SAR ADC is increased without any redundant cycles. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 4 mW from 1.2 V power supply with a SNDR > 6 6. 7 dB and S F D R > 8 2. 1 dB. The proposed ADC core occupies an active area of 0.048 mm2, and the corresponding FoM is 27.2 fJ/conversion-step at Nyquist rate. [ABSTRACT FROM AUTHOR]