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1 . Report
Imaging quantum interference in a monolayer Kitaev quantum spin liquid candidate
저자
by
Kohsaka, Y.
;
Akutagawa, S.
;
Omachi, S.
;
Iwamichi, Y.
;
Ono, T.
, et al.
소스
Open Access (Arxiv)
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7 . Report
Development of a Neutron Imaging Sensor using INTPIX4-SOI Pixelated Silicon Devices
저자
by
Kamiya, Y.
;
Miyoshi, T.
;
Iwase, H.
;
Inada, T.
;
Mizushima, A.
, et al.
소스
Nucl. Instrum. Methods A979, 164400 (2020)*
Open Access (Arxiv)
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7 . Academic Journal
Wetting of phase-separated droplets on plant vacuole membranes leads to a competition between tonoplast budding and nanotube formation
저자
by
Kusumaatmaja, Halim
;
May, Alexander I.
;
Feeney, Mistianne
;
McKenna, Joseph F.
;
Mizushima, Noboru
, et al.
소스
Proceedings of the National Academy of Sciences of the United States of America, 2021 Sep 01. 118(36), 1-3.
Full Text (PNAS)
Web of Science
Scopus
JCR 저널정보
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7 . Report
Improved measurement results for the Avogadro constant using a 28Si-enriched crystal
저자
by
Azuma, Y
;
Barat, P
;
Bartl, G
;
Bettin, H
;
Borys, M
, et al.
소스
Metrologia 52 (2015) 360-375
Open Access (Arxiv)
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7 . Conference
High performance CMOSFET technology for 45nm generation and scalability of stress-induced mobility enhancement technique
저자
by
Oishi, A.
;
Fujii, O.
;
Yokoyama, T.
;
Ota, K.
;
Sanuki, T.
, et al.
소스
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. International Electron Devices Meeting 2005 Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International. :229-232 2005
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7 . Conference
New stress inducing technique of epitaxial si on recessed S/D fabricated in substrate strained-si of [100]channel on rotated wafers
저자
by
Sanuki, T.
;
Tanaka, H.
;
Oota, K.
;
Fujii, O.
;
Yamaguchi, R.
, et al.
소스
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. International Electron Devices Meeting 2005 Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International. :501-504 2005
Full Text (IEEE)
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7 . Conference
Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length
저자
by
Okano, K.
;
Izumida, T.
;
Kawasaki, H.
;
Kaneko, A.
;
Yagishita, A.
, et al.
소스
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. International Electron Devices Meeting 2005 Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International. :721-724 2005
Full Text (IEEE)
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7 . Conference
Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm finfet with elevated source/drain extension
저자
by
Kaneko, A.
;
Yagishita, A.
;
Yahashi, K.
;
Kubota, T.
;
Omura, M.
, et al.
소스
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. International Electron Devices Meeting 2005 Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International. :844-847 2005
Full Text (IEEE)
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7 . Conference
Low power logic circuit and SRAM cell applications with silicon on depletion layer CMOS (SODEL CMOS) technology
저자
by
Inaba, S.
;
Nagano, H.
;
Miyano, K.
;
Mizushima, I.
;
Okayama, Y.
, et al.
소스
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) Custom integrated circuists Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004. :225-228 2004
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7 . Conference
Silicide technology for USJ in next technology node
저자
by
Suguro, K.
;
Iinuma, T.
;
Izuha, M.
;
Ohuchi, K.
;
Hokazono, A.
, et al.
소스
Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT. Junction technology Junction Technology, 2002. IWJT. Extended Abstracts of the Third International Workshop on. :67-70 2002
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