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1 . Academic Journal
Vigilanza globale: un termine alla ricerca di un contenuto. Un commento.
저자
by
T. GYOHTEN
.
소스
Moneta e Credito, Vol 51, Iss 201 (2014)
Open Access (DOAJ)
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3 . Academic Journal
Global supervision: a term in search of a content: A comment.
저자
by
T. GYOHTEN
.
소스
PSL Quarterly Review, Vol 51, Iss 204 (2014)
Open Access (DOAJ)
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3 .
Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor
저자
by
Katsumi Dosaka
;
Takeshi Kumaki
;
Yasuto Kuroda
;
Tetsushi Koide
;
Kazutami Arimoto
, et al.
소스
IEICE Transactions on Electronics
. :1409-1418
Web of Science
Scopus
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7 .
The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture
저자
by
Katsuya Mizumoto
;
K. Yoshida
;
Kazutami Arimoto
;
Y. Okuno
;
Katsumi Dosaka
, et al.
소스
IEEE Journal of Solid-State Circuits
. 42:804-812
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7 .
A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory
저자
by
Takashi Ipposhi
;
T. Gyohten
;
Fukashi Morishita
;
Hideyuki Noda
;
Isamu Hayashi
, et al.
소스
IEEE Journal of Solid-State Circuits
. 42:853-861
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7 .
A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI
저자
by
Hideyuki Noda
;
Shigeto Maegawa
;
T. Gyohten
;
Takashi Ipposhi
;
Mako Okamoto
, et al.
소스
IEICE Transactions on Electronics
. :765-771
Web of Science
Scopus
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7 .
The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture
저자
by
Katsuya Mizumoto
;
Katsumi Dosaka
;
Hiroyuki Kondo
;
K. Nakata
;
Kazutami Arimoto
, et al.
소스
IEEE Journal of Solid-State Circuits
. 42:183-192
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7 .
An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design
저자
by
T. Gyohten
;
Mako Okamoto
;
Isamu Hayashi
;
Hideyuki Noda
;
Katsumi Dosaka
, et al.
소스
IEICE Transactions on Electronics
. :1519-1525
Web of Science
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7 .
A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning
저자
by
M. Iida
;
M. Takeuchi
;
H. Otsuka
;
Y. Yamasaki
;
K. Shimakawa
, et al.
소스
IEEE Journal of Solid-State Circuits
. 40:2296-2304
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7 .
A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications
저자
by
H. Matsuoka
;
Atsushi Hachisuka
;
Hideyuki Noda
;
K. Shigeta
;
Kenji Anami
, et al.
소스
IEEE Journal of Solid-State Circuits
. 40:204-212
Full Text (IEEE)
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