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1 .
13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications
저자
by
Yen-Huei Chen
;
Wei-Min Chan
;
Wei-Cheng Wu
;
Hung-Jen Liao
;
Kuo-Hua Pan
, et al.
소스
2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
.
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7 .
19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme
저자
by
Yu-Der Chih
;
Jui-Jen Wu
;
Jonathan Chang
;
Chorng-Jung Lin
;
Meng-Fan Chang
, et al.
소스
ISSCC
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7 .
Ultra high density 3D via RRAM in pure 28nm CMOS process
저자
by
Yu-Cheng Liao
;
Chrong Jung Lin
;
Tzong-Sheng Chang
;
Yue-Der Chih
;
Min-Che Hsieh
, et al.
소스
2013 IEEE International Electron Devices Meeting
.
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7 .
Introduction to the Special Issue on the 2007 IEEE International Solid-State Circuits Conference
저자
by
David Harris
;
Ram Krishnamurthy
;
Sreedhar Natarajan
;
Siva G. Narendra
.
소스
IEEE Journal of Solid-State Circuits
. 43:3-5
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6 .
VLSI Circuits Symposium Celebrates 20th Anniversary in June
저자
by
Sreedhar Natarajan
.
소스
IEEE Solid-State Circuits Newsletter
. 12:72-74
Full Text (IEEE)
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3 .
A 55-nm, 0.86-Volt operation, 125MHz high speed, 75uA/MHz low power, wide voltage supply range 2M-bit split-gate embedded Flash
저자
by
Yue-Der Chih
;
Y. F. Lin
;
Sreedhar Natarajan
;
J. C. Wang
;
Caleb Yu-Sheng Cho
.
소스
2013 5th IEEE International Memory Workshop
.
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7 .
A 55-nm, 0.86-Volt operation, 75MHz high speed, 96uA/MHz low power, wide voltage supply range 2M-bit split-gate embedded Flash
저자
by
J. C. Wang
;
L. Huang
;
S. P. Liao
;
M. Weng
;
Y. F. Lin
, et al.
소스
VLSI-DAT
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7 .
A 180 MHz direct access read 4.6Mb embedded flash in 90nm technology operating under wide range power supply from 2.1V to 3.6V
저자
by
Sreedhar Natarajan
;
Ku-Feng Lin
;
Kai-Chun Lin
;
Yu-Der Chih
;
Hung-Chang Yu
.
소스
VLSI-DAT
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7 .
A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications
저자
by
Jun-Hao Chang
;
Chung-Cheng Wu
;
Sreedhar Natarajan
;
G. H. Chang
;
Shyue-Shyh Lin
, et al.
소스
ISSCC
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7 .
Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology
저자
by
Kai-Chun Lin
;
L.C. Tran
;
Chin-Yi Huang
;
Jun-Hao Chang
;
Yu-Der Chih
, et al.
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