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1 . Academic Journal
3-D Monolithic Stacking of Complementary-FET on CMOS for Next Generation Compute-In-Memory SRAM
저자
by
Md. Aftab Baig
;
Cheng-Jui Yeh
;
Shu-Wei Chang
;
Bo-Han Qiu
;
Xiao-Shan Huang
, et al.
소스
IEEE Journal of the Electron Devices Society, Vol 11, Pp 107-113 (2023)
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7 . Academic Journal
Random and Systematic Variation in Nanoscale Hf0.5Zr0.5O2 Ferroelectric FinFETs: Physical Origin and Neuromorphic Circuit Implications
저자
by
Sourav De
;
Md. Aftab Baig
;
Bo-Han Qiu
;
Franz Müller
;
Hoang-Hiep Le
, et al.
소스
Frontiers in Nanotechnology, Vol 3 (2022)
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7 . Academic Journal
Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter
저자
by
Po-Jung Sung
;
Chun-Jung Su
;
Shih-Hsuan Lo
;
Fu-Kuo Hsueh
;
Darsen D. Lu
, et al.
소스
IEEE Journal of the Electron Devices Society, Vol 8, Pp 474-480 (2020)
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7 . Conference
Low-temperature microwave annealing processes for future IC fabrication
저자
by
Yao-Jen Lee
;
Bo-An Tsai
;
Ta-Chun Cho
;
Fu-Kuo Hsueh
;
Po-Jung Sung
, et al.
소스
2014 IEEE International Nanoelectronics Conference (INEC) Nanoelectronics Conference (INEC), 2014 IEEE International. :1-4 Jul, 2014
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7 . Conference
A novel bottom-up Ag contact (30nm diameter and 6.5 aspect ratio) technology by electroplating for 1Xnm and beyond technology
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by
Chao-An Jong
;
Po-Jung Sung
;
Mei-Yi Lee
;
Fu-Ju Hou
;
Kehuey Wu
, et al.
소스
2011 International Electron Devices Meeting Electron Devices Meeting (IEDM), 2011 IEEE International. :7.6.1-7.6.4 Dec, 2011
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7 . Conference
Nearly defect-free Ge gate-all-around FETs on Si substrates
저자
by
Shu-Han Hsu
;
Chun-Lin Chu
;
Wen-Hsien Tu
;
Fu, Yen-Chun
;
Po-Jung Sung
, et al.
소스
2011 International Electron Devices Meeting Electron Devices Meeting (IEDM), 2011 IEEE International. :35.2.1-35.2.4 Dec, 2011
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7 .
First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications
저자
by
Shu-Wei Chang
;
Tsung-Han Lu
;
Cong-Yi Yang
;
Cheng-Jui Yeh
;
Min-Kun Huang
, et al.
소스
IEEE Transactions on Electron Devices
. 69:2101-2107
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7 .
(Invited) Layer Transfer Technology for Stacked Multi-Channel Semiconductor-on-Insulator Platform
저자
by
Yao-Jen Lee
;
Hiroyuki Ishii
;
Tatsuro Maeda
;
Po-Jung Sung
;
T.-Z. Hong
, et al.
소스
ECS Transactions
. 102:17-26
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7 .
Investigation on selectively etched SiGe and Si surface for Gate-All-Around CMOS devices fabrication
저자
by
Wei-Yuan Chang
;
Chun-Lin Chu
;
Guang-Li Luo
;
Yi-Shuo Huang
;
Chun-Hsiung Lin
, et al.
소스
2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
.
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7 . Academic Journal
Ultra-Shallow Junction Formation by Monolayer Doping Process in Single Crystalline Si and Ge for Future CMOS Devices.
저자
by
Shang-Shiun Chuang
;
Ta-Chun Cho
;
Po-Jung Sung
;
Kuo-Hsing Kao
;
Chen, Henry J. H.
, et al.
소스
ECS Journal of Solid State Science & Technology; 2017, Vol. 6 Issue 5, pP350-P355, 6p
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