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1 . Conference
34.2 A 21pJ/frame/pixel Imager and 34pJ/frame/pixel Image Processor for a Low-Vision Augmented-Reality Smart Contact Lens
저자
by
Singh, Rituraj
;
Bailey, Stevo
;
Chang, Phillip
;
Olyaei, Ashkan
;
Hekmat, Mohammad
, et al.
소스
2021 IEEE International Solid-State Circuits Conference (ISSCC) Solid-State Circuits Conference (ISSCC), 2021 IEEE International. 64:482-484 Feb, 2021
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7 . Conference
A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET
저자
by
Han, Jaeduk
;
Chang, Eric
;
Bailey, Stevo
;
Wang, Zhongkai
;
Bae, Woorham
, et al.
소스
2019 IEEE Custom Integrated Circuits Conference (CICC) Custom Integrated Circuits Conference (CICC), 2019 IEEE. :1-4 Apr, 2019
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7 . Conference
A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET
저자
by
Bailey, Stevo
;
Han, Jaeduk
;
Rigge, Paul
;
Lin, Richard
;
Chang, Eric
, et al.
소스
2018 IEEE Asian Solid-State Circuits Conference (A-SSCC) Solid-State Circuits Conference (A-SSCC), 2018 IEEE Asian. :285-288 Nov, 2018
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7 . Conference
A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET
저자
by
Wang, Angie
;
Bae, Woorham
;
Han, Jaeduk
;
Bailey, Stevo
;
Rigge, Paul
, et al.
소스
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2018 - IEEE 44th. :322-325 Sep, 2018
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7 . Conference
A 28nm FDSOI 8192-point digital ASIC spectrometer from a Chisel generator
저자
by
Bailey, Stevo
;
Wright, John
;
Mehta, Nandish
;
Hochman, Rachel
;
Jarnot, Robert
, et al.
소스
2018 IEEE Custom Integrated Circuits Conference (CICC) Custom Integrated Circuits Conference (CICC), 2018 IEEE. :1-4 Apr, 2018
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7 . Conference
A 0.37mm2 LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5k FFT accelerator integrated with a RISC-V core in 16nm FinFET
저자
by
Wang, Angie
;
Richards, Brian
;
Dabbelt, Palmer
;
Mao, Howard
;
Bailey, Stevo
, et al.
소스
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Solid-State Circuits Conference (A-SSCC), 2017 IEEE Asian. :305-308 Nov, 2017
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7 . Conference
Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC
저자
by
Keller, Ben
;
Cochet, Martin
;
Zimmer, Brian
;
Lee, Yunsup
;
Blagojevic, Milovan
, et al.
소스
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference European Solid-State Circuits Conference, ESSCIRC Conference 2016: 42nd. :269-272 Sep, 2016
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7 . Conference
Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking
저자
by
Lee, Yunsup
;
Zimmer, Brian
;
Waterman, Andrew
;
Puggelli, Alberto
;
Kwak, Jaehwa
, et al.
소스
2015 IEEE Hot Chips 27 Symposium (HCS) Hot Chips 27 Symposium (HCS), 2015 IEEE. :1-45 Aug, 2015
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7 . Academic Journal
An Agile Approach to Building RISC-V Microprocessors
저자
by
Lee, Yunsup
;
Waterman, Andrew
;
Cook, Henry
;
Zimmer, Brian
;
Keller, Ben
, et al.
소스
IEEE Micro Micro, IEEE. 36(2):8-20 Jan, 2016
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7 . Conference
A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI
저자
by
Zimmer, Brian
;
Lee, Yunsup
;
Puggelli, Alberto
;
Kwak, Jaehwa
;
Jevtic, Ruzica
, et al.
소스
2015 Symposium on VLSI Circuits (VLSI Circuits) VLSI Circuits (VLSI Circuits), 2015 Symposium on. :C316-C317 Jun, 2015
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