An 18-bit SAR ADC with Mixed DAC and Capacitive Recombination Calibration
- Resource Type
- Original Paper
- Authors
- Li, Dagang; Li, Zehong; Chen, Zhuorui; Qi, Xiaohu; Fan, Hua; Zhou, Wei; Li, Wei; Wang, Ce; Cui, Chen; Ma, Keyan; Feng, Quanyuan; Wei, Qi; Guo, Xinkai; Sun, Yan
- Source
- Circuits, Systems, and Signal Processing. 43(7):4021-4049
- Subject
- Analog-to-digital converter (ADC)
Successive approximation register (SAR)
Capacitive recombination
Foreground calibration
Output offset storage
- Language
- English
- ISSN
- 0278-081X
1531-5878
This paper presents a high-resolution 18-bit SAR ADC with a high 10-bit capacitor DAC and a low 8-bit resistor DAC. The total required number of the unit capacitors is decreased to 512. Foreground digital calibration based on capacitive recombination is introduced to improve linearity. Preamplifiers and output offset storage(OOS) enhance the noise and offset performance of the comparator. As a result, the design under 180 nm process achieves a signal-to-noise and distortion ratio(SNDR) of 105.5dB and a spurious-free dynamic range (SFDR) of 116.3dB under 1 MS/s sampling rate with a single channel. The effective number of bits (ENOB) can reach 17.23 bits with a Nyquist-rate input while consuming 46 mW from a 5 V supply. The resultant Schreier and Walden figures of merit (FoM) are 178.92 dB and 295.34 fJ/conversion-step, respectively. The proposed SAR ADC occupies an actual area of 3850 μμm by 2810 μμm.