In this paper, three approximate multiplier architectures are proposed: area-optimized approximate multiplier (AOM), power-optimized approximate multiplier (POM), and power- and area-optimized approximate multiplier (PAOM). These designs are implemented using speculative Han–Carlson adder and compressor-based multiplier blocks. Han–Carlson adder is used as the basic adder block in the final addition stage of all the three approximate multiplier designs. Different types of compressors (3:2, 4:2, 5:2, 6:2, 7:2, 8:2) are used for the implementation of the energy-efficient approximate multiplier blocks. All the simulations are performed on VIVADO design tool. Also, the designed multipliers are validated for image blending (an error-tolerant) application. The proposed power optimization approximate multiplier shows 0.86%, 10.54% PSNR improvement in comparison with area optimization approximate multiplier and power and area optimization approximate multiplier, respectively.