Circuit arrangement, a method for forming a circuit arrangement, and method for integrity checking
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- Patent
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A circuit arrangement is provided, the circuit arrangement including a processor; a memory circuit connected to the processor, wherein the processor is configured to access the memory circuit; a blocking circuit configured to generate one or more random wait state signals which prevent the processor from accessing the memory circuit; and an integrity checking circuit configured to check the memory circuit during a wait state period of the one or more random wait state signals.