SELF-TIMED CLOCKED ANALOG TO DIGITAL CONVERTER
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- Patent
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An SAR analog-to-digital converter performs bit decisions in each of a plurality of clock cycles A sense circuit monitors signals input to a latch within a comparator of the ADC and, when the signals are sufficient to establish a bit decision, the sense circuit terminates a currently active clock cycle causes a bit decision to occur in advance of a normal expiration of the clock cycle. If the signals are insufficient to establish a bit decision prior to a default expiration time of the clock cycle, the clock cycle concludes at the default expiration time.