Inter-Layer Dielectric Engineering for Monolithic Stacking 4F2-2 T0C DRAM with Channel-All-Around (CAA) IGZO FET to Achieve Good Reliability (>104 s Bias Stress, >1012 Cycles Endurance)
- Resource Type
- Conference
- Authors
- Chen, Chuanke; Duan, Xinlv; Yang, Guanhua; Lu, Congyan; Geng, Di; Li, Ling; Liu, Ming
- Source
- 2022 International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2022 International. :26.5.1-26.5.4 Dec, 2022
- Subject
- Bioengineering
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Fields, Waves and Electromagnetics
Photonics and Electrooptics
Power, Energy and Industry Applications
Robotics and Control Systems
Signal Processing and Analysis
Degradation
Three-dimensional displays
Field effect transistors
Stacking
Hydrogen
Random access memory
Logic gates
- Language
- ISSN
- 2156-017X
To address the stacking requirement of $4F^{2}-2$ T0C DRAM with vertical channel-all-around (CAA) IGZO FETs, for the first time, the effect of inter-layer dielectric (ILD) on CAA-IGZO FETs has been studied by varying dielectric material and process. By using optimized ILD and IGZO deposition cycle ratio, CAA-IGZO FET with high reliability is obtained. The optimized device exhibits a ${V}_{th}$ shift of less than 25 mV after $10^{4}s$ bias stress and no significant degradation after 10 12 cycles endurance. Our results provide an important reference for facilitating the monolithic stacking of multilayer IGZO FETs to realize 3D DRAM.