A Parallel Configuration Model for Reducing the Run-Time Reconfiguration Overhead
- Resource Type
- Conference
- Authors
- Yang Qu; Soininen, J.-P.; Nurmi, J.
- Source
- Proceedings of the Design Automation & Test in Europe Conference Design, Automation and Test in Europe Design, Automation and Test in Europe, 2006. DATE '06. Proceedings. 1:1-6 2006
- Subject
- Computing and Processing
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Runtime
Tiles
Multitasking
Reconfigurable logic
Silicon
Delay
Degradation
System performance
Random access memory
Prefetching
- Language
- ISSN
- 1530-1591
1558-1101
Multitasking on reconfigurable logic can achieve very high silicon reusability. However, configuration latency is a major limitation and it can largely degrade the system performance. One reason is that tasks can run in parallel but configurations of the tasks can be done only in sequence. This work presents a novel configuration model to enable configuration parallelism. It consists of multiple homogeneous tiles and each tile has its own configuration SRAM that can be individually accessed. Thus multiple configuration controllers can load tasks in parallel and more speedups can be achieved. We used a prefetch scheduling technique to evaluate the model with randomly generated tasks. The experiment results reveal that in average using multiple controllers can reduce the configuration overheads by 21%. Compared to best cases of using multiple tiles with a single controller, additional 40% speedup can be achieved using multiple controllers.