A 4×112 Gb/s ADC-DSP Based Multistandard Receiver in 7nm FinFET
- Resource Type
- Conference
- Authors
- Lin, Haidang.; Boecker, Charles.; Hossain, Masum; Tangirala, Shankar; Vu, Roxanne; Vamvakos, Socrates; Groen, Eric; Li, Simon; Choudhary, Prashant; Wang, Nanyan; Shibata, Masumi; Taghavi, Hossein; van Ierssel, Marcus; Maniyar, AdilHussain; Wodkowski, Adam; Nguyen, Nhat; Desai, Shaishav
- Source
- 2020 IEEE Symposium on VLSI Circuits VLSI Circuits, 2020 IEEE Symposium. :1-2 Jun, 2020
- Subject
- Components, Circuits, Devices and Systems
Receivers
Timing
FinFETs
Equalizers
Signal to noise ratio
Loss measurement
Jitter
DFE-FFE
PAM-4
112 Gb/s
- Language
- ISSN
- 2158-5636
This paper describes a 4 × 112 Gb/s digital receiver targeting Long Reach (LR) channels. The discrete time front-end overcomes gain-BW limitations to provide 10+dB gain at 28GHz. A 56GS/s ADC then converts the signal to 6-b digital consuming only 195mW. The following DFE-FFE based digital equalizer is capable of compensating 36 dB loss achieving BER of 2e-5. Furthermore, TDC and ISI filter based low latency timing recovery meets jitter tolerance specs over a wide range of data rates (25Gb/s NRZ to 106.25Gb/s PAM-4). The overall receiver consumes 338mW with 3.18pJ/bit energy efficiency