A 10b 320MS/s self-calibrated pipeline ADC
- Resource Type
- Conference
- Authors
- Chen, Hung-Wei; Shen, Wei-Ting; Cheng, Wei-Chih; Chen, Hsin-Shu
- Source
- 2010 IEEE Asian Solid-State Circuits Conference Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian. :1-4 Nov, 2010
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Calibration
Capacitors
Clocks
Pipelines
Bandwidth
Registers
Gain
Pipeline analog-to-digital converter (ADC)
interstage gain
low-gain opamp
self-calibrated
- Language
A high-speed low-power self-calibrated pipeline ADC is presented. Gain error due to low-gain opamp used in multiplying DAC (MDAC) is corrected by the proposed foreground calibration technique. It adjusts the inter-stage gain by connecting a calibration capacitor into the MDAC positive feedback path. It only requires 168 clock cycles to complete the calibration without external precise references. The calibration circuit does not consume power during normal conversion. The prototype ADC in 90nm low-power CMOS technology achieves conversion rate of 320MS/s with peak SFDR and SNDR of 66.7dB and 54.2dB. The total power dissipation is 42mW and it occupies an active chip area of 0.21mm 2 Its figure-of-merit (FOM) is 442fJ/conversion-step.