A noise-shaping SAR ADC with dual error-feedback paths and alternate DACs
- Resource Type
- Conference
- Authors
- Yang, Jiaqi; Zhang, Jili; Bai, Xuefei; Lin, Fujiang
- Source
- 2017 IEEE 12th International Conference on ASIC (ASICON) ASIC (ASICON), 2017 IEEE 12th International Conference on. :291-294 Oct, 2017
- Subject
- Components, Circuits, Devices and Systems
Noise shaping
Quantization (signal)
Switches
Capacitors
Transfer functions
CMOS process
Clocks
Analog-to-digital converters
Successive approximation register
Noise-shaping
- Language
This paper presents an opamp-free solution to implement noise-shaping technique in successive-approximation register (SAR) ADCs. With delayed quantization error applied to both comparator and sample-hold circuit through dual feedback paths, effective noise-shaping is achieved using a passive loop filter. Two identical switched-capacitors DACs are employed to perform voltage approximation and to maintain the quantization error alternately. A SAR ADC adopting the proposed opamp-free noise-shaping solution is designed in a 0.18-μm CMOS process. Post-layout simulation exhibits 10.6-bit accuracy at 48MS/s sampling frequency based on 8-bit DAC when the oversampling rate is 4. The proposed ADC dissipates 451μW from a 1.5-V supply and achieves a Walden FOM of 24.2 fJ/conversion-step.