Optimal body biasing for maximizing circuit performance in 65nm CMOS technology
- Resource Type
- Conference
- Authors
- Moradi, Farshad; Cao, Tuan Vu; Wisland, Dag T.; Aunet, Snorre; Mahmoodi, Hamid
- Source
- 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS) Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on. :1-4 Aug, 2011
- Subject
- Components, Circuits, Devices and Systems
Computing and Processing
Communication, Networking and Broadcast Technologies
Equations
CMOS technology
Transistors
MOS devices
Wireless communication
CMOS integrated circuits
Reduced instruction set computing
Body-biasing
65nm
nano-scale
sub-threshold
- Language
- ISSN
- 1548-3746
1558-3899
In this paper, the effect of body-biasing technique in 65nm CMOS technology is investigated. The optimum body voltage in different process corners to get the maximum ON current is acquired using ST 65nm technology. The effectiveness of body biasing technique is investigated for sub- and super-threshold designs. We show that for higher supply voltages, there is an optimum body voltage to get the maximum performance. The results for some Flip-Flops are shown.