Embedded system-on-chip design of atrial fibrillation classifier
- Resource Type
- Conference
- Authors
- Lim, Huey Woan; Hau, Yuan Wen; Othman, Mohd Afzan; Lim, Chiao Wen
- Source
- 2017 International SoC Design Conference (ISOCC) SoC Design Conference (ISOCC), 2017 International. :90-91 Nov, 2017
- Subject
- Components, Circuits, Devices and Systems
Electrocardiography
Heart
Artificial neural networks
Atrial fibrillation
Rhythm
Computer architecture
Detection algorithms
Atrial fibrillation (AFIB)
artificial neural network (ANN)
FPGA
System-on-chip (SoC)
wavelet transform
- Language
Atrial Fibrillation (AFIB) is one of the major risk factors of stroke and heart failure which can be observed from the electrocardiogram (ECG). This paper presents an embedded system-on-chip (SoC) architecture design of AFIB detection based on stationary wavelet transform (SWT) and artificial neural network (ANN) algorithm for heart screening propose. The architecture is designed using the hardware/software co-design technique and prototyped on Altera DE2-115 FPGA platform. Hardware acceleration of compute intensive FFT operation is also carried out to enhance computation timing performance. The whole system consumes 40,830 LEs of Altera Cyclone-IV FPGA device. The total computation time of AFIB classifier is 22 seconds for 10 seconds ECG input data with the accuracy of 95.3% which able to detect AFIB rhythm, normal sinus rhythm, and non-AFIB rhythm.