Implementing custom machine learning (ML) accelerators involves running thousands if not millions of clock cycles of simulations per training epoch and is infeasible in low-level commercial EDA tools. This task becomes even more difficult if the ML hardware is asynchronous rather than clocked. Asynchronous designs provide towards significant energy-efficiency, which is the most important challenge in artificial intelligence (AI) today. Field programmable gate array (FPGA) based prototyping could help make design automation feasible, but existing FPGAs are clocked, and adapting them for implementing asynchronous circuits is challenging. This is primarily because FPGAs violate the usual timing constraints in those circuits, such as isochronic forks. This paper addresses the core aspect of design automation of asynchronous circuits through FPGAs by solving the problem of mapping critical timing constraints while retaining important delay-insensitivity properties in a range of algorithms compatible with the FPGA synthesis tools. Our case study involves circuits implementing a novel ML algorithm, known as the Tsetlin machine, the central part of a TM, and majority voting are synthesized. Different scales of circuits with up to 9513 LUTs implement the clause generator.