Wafer-Level LICCDM Device Testing
- Resource Type
- Conference
- Authors
- Simicic, Marko; Wu, Wei-Min; Claes, Dieter; Tamura, Shinichi; Shimada, Yohei; Sawada, Masanori; Chen, Shih-Hung
- Source
- 2021 43rd Annual EOS/ESD Symposium (EOS/ESD) EOS/ESD Symposium (EOS/ESD), 2021 43rd Annual. 43:1-8 Sep, 2021
- Subject
- Aerospace
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Engineering Profession
Fields, Waves and Electromagnetics
General Topics for Engineers
Photonics and Electrooptics
Power, Energy and Industry Applications
Robotics and Control Systems
Signal Processing and Analysis
Integrated circuits
Three-dimensional displays
Current measurement
Stacking
Size measurement
Electrostatic discharges
Dielectric measurement
- Language
With the integrated circuit technology evolution towards 25D and 3D stacking, wafer-level and bare-die-level electrostatic discharge testing is becoming a necessity. In this work, we use our Low-Impedance Contact CDM tester to measure integrated circuit products and assess the possibilities and potential issues of CDM testing of wafers and bare dies.