A Synchronized 35 GHz Divide-by-5 TSPC Flip-Flop Clock Divider in 22 nm FDSOI
- Resource Type
- Conference
- Authors
- Probst, Florian; Engelmann, Andre; Weigel, Robert
- Source
- 2023 Asia-Pacific Microwave Conference (APMC) Microwave Conference (APMC), 2023 Asia-Pacific. :212-214 Dec, 2023
- Subject
- Aerospace
Bioengineering
Components, Circuits, Devices and Systems
Fields, Waves and Electromagnetics
Voltage measurement
Power demand
Silicon-on-insulator
Frequency conversion
Synchronization
Frequency synchronization
Clocks
Clock divider
fully-depleted silicon on insulator (FDSOI)
mixed-signal circuits
true single-phase-clock (TSPC)
- Language
This work proposes an integrated divide-by-five clock divider based on a true single-phase-clock (TSPC) ring buffer. Fabricated in a 22 nm fully-depleted silicon on insulator (FDSOI) technology, the circuit can synchronously divide input frequencies up to 35 GHz, where it exhibits a power consumption of 1.35 mW. The divider core consumes an area of $12.1 \times 2.8 \mathrm{~m}^{2}$ and is integrated into a multi-circuit break out chip of $600 \times 530 \mathrm{~mm}^{2}$. It is designed to extend high-speed mm-wave circuits by a digital block operating synchronously at one-fifth of the clock rate.