FPGA-based HDLC Controller Design and Communication Implementation in Normal Response Mode
- Resource Type
- Conference
- Authors
- Huang, Chengjie; Zhong, Xiaoling; Song, Qishun; Chen, Shuhang
- Source
- 2022 IEEE 4th International Conference on Power, Intelligent Computing and Systems (ICPICS) Power, Intelligent Computing and Systems (ICPICS), 2022 IEEE 4th International Conference on. :112-115 Jul, 2022
- Subject
- Computing and Processing
Power, Energy and Industry Applications
Robotics and Control Systems
Signal Processing and Analysis
Semiconductor device measurement
Power measurement
Programming
Hardware
Data models
Software
Main-secondary
HDLC protocol
FPGA
CRC
IO interface
- Language
High-Level Data Link Control is a bit-oriented link-layer transmission protocol widely used in communication and measurement and control equipment with high reliability and transparent transmission. In order to solve the problems of low flexibility of ASIC chip and high CPU resource consumption of software implementation, this paper designs an HDLC controller with Verilog HDL in the Xilinx platform and completed the module simulation verification and hardware test of communication under the normal response mode; the results show that the controller has stable data transmission, low resource consumption, and robust error correction capability.