This paper presents a low-dropout regulator that has been implemented in a 180 nm standard CMOS technology. The regulator utilizes a voltage-difference-to-time converter and adaptive-power transistors to achieve low supply voltage and wide load current operation. By combining the benefits of analog and digital LDO, this design maintains good regulation performance and ensures output ripple-less conditions. An undershoot reduction circuit has also been incorporated to significantly reduce the transient voltage spike during load changes. The simulated results, the proposed LDO demonstrates a wide operation range with an input voltage range of 0.6-1.2 V and a load current of 10 $\mu-200\text{mA}$. Additionally, the simulated undershoot is 145 m V, and the output voltage recovers within 0.57 $\mu \mathrm{s}$ when the load current steps from 1 mA to 200 mA with a 1 ns edge time. The figure of merit for this design is as low as 5 ps.