Self-Timed Pipeline with Variable Stage Number*
- Resource Type
- Conference
- Authors
- Sokolov, Igor A.; Rogdestvenski, Yuri V.; Stepchenkov, Yuri A.; Diachenko, Denis Y.; Diachenko, Yuri G.; Plekhanov, Leonid P.
- Source
- 2023 Seminar on Networks, Circuits and Systems (NCS) Networks, Circuits and Systems (NCS), 2023 Seminar on. :160-165 Nov, 2023
- Subject
- Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Seminars
Circuits and systems
Pipelines
Switches
Organizations
Data processing
self-timed circuit
pipeline stage
indication
performance
latency
bypass
- Language
The paper analyzes the problem of improving the self-timed pipeline’s performance. The paper considers possible options for reducing the pipeline latency by decreasing the number of actively operating stages when certain conditions occur, determined by the processed data value or an external signal. One stage bypassing becomes appropriate if it occurs in at least 64% of data processing operations, while two stage bypassing decreases the average pipeline latency if it occurs in 50% of operations.