Compute-in-Memory with SAR ADC and 2T1C DRAM for MAC Operations
- Resource Type
- Conference
- Authors
- Jang, Tae Eun; Lee, Kyu Hyun; Kim, Gi Yeol; Yun, Su Yeon; Youn, Da-Hyeon; Choi, Hyunggu; Kim, Jihyang; Kim, Soo Youn; Song, Minkyu
- Source
- 2024 International Conference on Electronics, Information, and Communication (ICEIC) Electronics, Information, and Communication (ICEIC), 2024 International Conference on. :1-3 Jan, 2024
- Subject
- Bioengineering
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Fields, Waves and Electromagnetics
Photonics and Electrooptics
Codes
Architecture
Microprocessors
Kirchhoff's Law
Random access memory
Computer architecture
In-memory computing
2T1C DRAM
Process-In-Memory
Compute-In-Memory
Successive approximation analog-to-digital converter
- Language
- ISSN
- 2767-7699
This paper presents a compute-in-memory (CIM) architecture for MAC operation using 2T1 C dynamic random access memory (DRAM) and a successive-approximation analog-to-digital converter (SAR ADC). The proposed design features CIM analog multiplication and summation architecture consisting of a digital-to-time converter (DTC) and SAR ADC. The DTC converts the input code into clock-based pulse width, and the calculation can be done by passing through pulse into a 2T1C DRAM array in parallel. The proposed structure is implemented using a 28-nm CMOS process, operates four parallel $2-bit\times 4-bit$ multiplication and total summation simultaneously, and a single calculation requires 140ns for 100MHz system clock frequency.