In several processing units, the MAC is an essential module. Current leakage power reduction techniques for the design of High Performance and Ultra Low Power (HP-ULP) MAC units are not enough. The best approach for constructing subthreshold circuits is body biasing. Adaptive forward and reverse body biasing (AFR-B) methods are suggested to forward ON devices of body bias by reducing threshold voltage to increase speed by increasing the drive current and the reverse body bias of OFF devices, the threshold voltage is raised, reducing the leakage current. With set bias voltages, each PMOS and NMOS bias voltage is individually tuned. Both PMOS and NMOS bias voltages are similar in magnitude. With parallel multiplier, adders and body biasing methods, a MAC device is built.In the 45nm technology with CMOS logic, an 8-bit MAC device with parallel multiplier and adder is implemented. Adder and multiplier are first designed and then used in the top module with and without body biasing technique. With the body biasing technique, the entire design is applied and contrasts are made between the basic and proposed new MAC architecture. Better outcomes are obtained with regard to power and delay in proposed design. With 1V and 400mV supply voltage, the MAC with body biassing architecture is analysed.