A 0.9 pJ/bit, 12.8 GByte/s WideIO memory interface in a 3D-IC NoC-based MPSoC
- Resource Type
- Conference
- Authors
- Dutoit, Denis; Bernard, Christian; Cheramy, Severine; Clermidy, Fabien; Thonnart, Yvain; Vivet, Pascal; Freund, Christian; Guerin, Vincent; Guilhot, Stephane; Lecomte, Stephane; Qualizza, Gianni; Pruvost, Julien; Dodo, Yves; Hotelier, Nicolas; Michailos, Jean
- Source
- 2013 Symposium on VLSI Technology VLSI Technology (VLSIT), 2013 Symposium on. :C22-C23 Jun, 2013
- Subject
- Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
System-on-chip
Random access memory
Integrated circuit interconnections
Bandwidth
Mobile communication
Memory management
- Language
- ISSN
- 0743-1562
2158-9682
3D Integrated Circuit (3D-IC) opens architecture opportunities for improved SoC-to-memory interconnect bandwidth between dies. This paper presents the design of a two-tier 3D-IC composed of one NoC-based MPSoC and one multi-channel WideIO mobile SDRAM stacked in a face-to-back configuration. Measurements of the 3D-IC show that the targeted 12.8 GByte/s bandwidth is achieved in worst case conditions, while offering a 0.9 pJ/bit 3D I/O link power efficiency.