An Ising Model-Based Annealing Processor With 1024 Fully Connected Spins for Combinatorial Optimization Problems
- Resource Type
- Periodical
- Authors
- Huang, Z.; Jiang, D.; Wang, X.; Yao, E.
- Source
- IEEE Transactions on Circuits and Systems II: Express Briefs IEEE Trans. Circuits Syst. II Circuits and Systems II: Express Briefs, IEEE Transactions on. 70(8):3074-3078 Aug, 2023
- Subject
- Components, Circuits, Devices and Systems
Annealing
Schedules
Turbo codes
Simulated annealing
Semiconductor device modeling
Hardware
Generators
Ising model
simulated annealing
fully connected
combinatorial optimization problems
- Language
- ISSN
- 1549-7747
1558-3791
This brief presents a novel annealing processor (AP) design with 1024 fully-connected spins based on a modified Ising model annealing algorithm for combinatorial optimization problems. By adopting the proposed Turbo code-based interleaved random sequence generator (TCSG) and multi-spin update method, the memory usage is made considerable reduction and multi-spin parallel update is supported. The prototype is implemented using FPGA with the operation frequency of 100 MHz. We tested our design on various G-set problems with an average cut accuracy of 99.19% achieved. The proposed design outperforms the CPU-based method by achieving a max speedup of $1099\times $ .