A 100MS/s 12 Bit SAR-assisted Pipeline ADC with Gain-enhanced Fully Differential Ring Amplifier
- Resource Type
- Conference
- Authors
- Fu, Yecong; Jian, Mingchao; Zheng, Jiwei; Guo, Chunbing
- Source
- 2023 IEEE MTT-S International Wireless Symposium (IWS) Wireless Symposium (IWS), 2023 IEEE MTT-S International. :1-3 May, 2023
- Subject
- Fields, Waves and Electromagnetics
Signal Processing and Analysis
Wireless communication
Simulation
Pipelines
Prototypes
CMOS technology
Standards
- Language
A 12 bit 100 MS/s SAR-assisted pipeline ADC with a 6-bit SAR ADC for the first stage and a 7-bit SAR ADC for the second stage is presented. The sub-ADCs adopt the upper plate sampling asynchronous SAR logic. The gain-enhanced fully differential ring amplifier acts as a residue amplifier, providing high-precision settling and accommodating large signal swings. The cascoded output stages are designed in the ring amplifier to enhance the closed loop accuracy. A prototype ADC has been designed and simulated using TSMC65nm CMOS technology, and it operates with a standard 1.2 V supply voltage.The SNDR and ENOB is 63.6dB and 10.28bit respectively from the simulation results, with a Nyquist frequency input sampled at 100 MS/s. The ADC achieves a FoM of 32.01 fJ/conversion-step.