This work presents a fully synthesizable DPLL with a feedforward phase noise cancellation (FPNC) path. The gain mismatch between the FPNC path components has been calibrated digitally in the background against process, voltage, and temperature (PVT) variations. As a result, the rms value of the absolute jitter was reduced over different conditions beyond the DPLL stability barrier. A prototype chip with an area of 0.105mm 2 was fabricated in 65nm CMOS technology. The measurements showed a jitter reduction at 1. 0GHz output frequency from 1. 0ps to 753fs at the cost of 0. 7mW extra power consumption and FoM improvement from -234.4dB to -236dB. Also, similar improvements were measured under different voltages, chips, and output frequencies.