A 2.5 GHz CMOS dual-modulus prescaler for RF frequency synthesizer
- Resource Type
- Conference
- Authors
- Wen-Rong Yang; Jia-Lin Lao; Fen Ran; Jian Wang
- Source
- Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004. Solid-state and integrated circuits technology Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on. 2:1547-1550 vol.2 2004
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Radio frequency
Frequency synthesizers
CMOS technology
Counting circuits
Phase locked loops
Voltage-controlled oscillators
Gallium arsenide
CMOS logic circuits
Noise reduction
RNA
- Language
A high-speed dual-modulus divide-by-32/33 prescaler has been developed in a 0.25 /spl mu/m CMOS technology. The source-coupled logic (SCL) structure is used to reduce the switching noise and to ameliorate the power-speed tradeoff. The proposed prescaler can operate at high frequency with a low-power consumption. Based on the 2.5V 0.25 /spl mu/m CMOS model, simulation results indicate that the maximum input frequency of the prescaler is up to 3.2 GHz. Running at a power supply of 2.5V, the circuit consumes only 4.6 mA at input frequency of 2.5 GHz.