A high-speed divide-by-32/33 frequency divider in 0.25/spl mu/m CMOS technology
- Resource Type
- Conference
- Authors
- Wen-Rong Yang; Jia-Lin Cao; Feng Ran; Ting-Gao Qing
- Source
- ICMMT 4th International Conference on, Proceedings Microwave and Millimeter Wave Technology, 2004. Microwave and millimeter wave technology Microwave and Millimeter Wave Technology, 2004. ICMMT 4th International Conference on, Proceedings. :554-557 2004
- Subject
- Engineered Materials, Dielectrics and Plasmas
Fields, Waves and Electromagnetics
Aerospace
Communication, Networking and Broadcast Technologies
Photonics and Electrooptics
CMOS technology
Frequency conversion
Frequency synthesizers
Counting circuits
Flip-flops
Circuit noise
Voltage-controlled oscillators
Gallium arsenide
Energy consumption
CMOS logic circuits
- Language
A high-speed divide-by-32/33 frequency divider has been developed in a 0.25/spl mu/m CMOS technology. The source-coupled logic (SCL) structure is used to reduce the switching noise and to ameliorate the power-speed tradeoff. The proposed divider can operate at high frequency with a low-power consumption. Based on the 2.5V 0.25/spl mu/m CMOS model, simulation results indicate that the maximum input frequency of the divider is up to 3.2GHz. Running at a power supply of 2.5V, the circuit consumes only 4.6mA at input frequency of 2.5GHz.