Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors
- Resource Type
- Conference
- Authors
- Doyle, Bruce A.; Loke, Alvin L. S.; Maheshwari, Sanjeev K.; Wang, Charles L.; Fischette, Dennis M.; Cooper, Jeffrey G.; Aggarwal, Sanjeev K.; Wee, Tin Tin; Lackey, Chad O.; Kedarnath, Harishkumar S.; Oshima, Michael M.; Talbot, Gerry R.; Fang, Emerson S.
- Source
- IEEE Asian Solid-State Circuits Conference 2011 Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian. :133-136 Nov, 2011
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Jitter
Clocks
Phase locked loops
Program processors
Frequency modulation
Bandwidth
Bit error rate
- Language
We present an 8.0-Gb/s HyperTransport™ technology I/O built in a 32-nm SOI-CMOS processor for high-performance servers. Based on a 45-nm design that caps at 6.4 Gb/s, the 32-nm transceiver achieves up to 8.0 Gb/s over long-reach board channels. Key enhancements include a high-bandwidth (>200 MHz) PLL to attenuate high-frequency jitter in the received forwarded clock and redesigned power-hungry circuits to operate at 8.0 Gb/s within the existing 45-nm package thermal limit.