A "system on a chip" is described, which integrates 16 Mbits of DRAM, digital logic, SRAM, three PLLs, and a triple video digital-to-analog converter in a 0.5 micron CMOS DRAM process. Application specific integrated circuit (ASIC) techniques are employed, using multiple DRAM macros with built-in self test (BIST), full level-sensitive scan design (LSSD) logic, and externally accessible analog circuitry. Issues regarding functional debugging, DRAM macro isolation and low cost manufacturing test using only a logic tester are described.