Based on Gate Diffusion Input (GDI) and Conventional Complementary Metal-Oxide Semiconductor (CCMOS) logic, this study offers a full-swing high-speed hybrid Full Adder (FA) cell. The design was evaluated and compared to standard ten full adder designs for their key significance in the real-time applications. The implementation is done using the Cadence tool in the 18 nm FINFET module. The small size of MOSFETs (less than 28nm nanometers) has caused certain operating issues in recent years, such as enhanced gate-oxide leakage, amplified junction leakage, strong sub-threshold conduction, and lowered output resistance. To solve the aforesaid issues, FinFET offers the benefits of an increase in the operating speed, lower power consumption, decreased static leakage current, which is utilised to realise the majority of the applications by replacing MOSFET. Considering the attractive characteristics of FinFETs, 10 standard full adder cells have been designed and tested using FinFETs. In terms of speed and power delay product, the proposed design shows a significant improvement (PDP). The limitations of the proposed models are validated by increasing the adder cells to the maximum number of 64bits.