Split Wisely: When Work Partitioning is Energy-Optimal on Heterogeneous Hardware
- Resource Type
- Conference
- Authors
- Mitra, Gaurav; Haigh, Andrew; Varghese, Anish; Angove, Luke; Rendell, Alistair P.
- Source
- 2016 IEEE 18th International Conference on High Performance Computing and Communications; IEEE 14th International Conference on Smart City; IEEE 2nd International Conference on Data Science and Systems (HPCC/SmartCity/DSS) HPCC-SMARTCITY-DSS High Performance Computing and Communications; IEEE 14th International Conference on Smart City; IEEE 2nd International Conference on Data Science and Systems (HPCC/SmartCity/DSS), 2016 IEEE 18th International Conference on. :781-788 Dec, 2016
- Subject
- Communication, Networking and Broadcast Technologies
Computing and Processing
Power measurement
Graphics processing units
Energy measurement
Current measurement
Predictive models
Computational modeling
System-on-chip
Energy usage model
SoC
NVIDIA
Tegra X1
Tegra K1
K20
K80
Load balancing
Energy efficiency
Intel
Haswell
Sandy bridge
uCurrent
Power Measurement
- Language
Heterogeneous System-on-Chip (SoC) processors are increasingly gaining traction in the High Performance Computing (HPC) community as alternate building blocks for future exascale systems. Key issues relating to their promise of energy efficiency include i) absolute performance, ii) finding an energy-optimal balance in the use of different on-chip devices and iii) understanding the performance-energy trade-offs while using different on-chip devices. In this paper we explore these issues through an energy usage model designed to predict the existence of an energy-optimal work partition between different processing elements on heterogeneous systems for any application. We validate our model by measuring performance and energy consumption of matrix multiplication on the NVIDIA Tegra K1 and X1 systems. An environment for monitoring and responding to energy usage is also outlined and used to perform high resolution measurements. Comparisons are drawn with conventional HPC systems housing Intel Xeon CPUs alongside NVIDIA GPUs.