A 12 bit 1 MHz ACD with 1 mW power consumption
- Resource Type
- Conference
- Authors
- Satou, K.; Tsuji, R.; Sahoda, M.; Otsuka, H.; Mori, K.; Iida, T.
- Source
- Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94 Custom integrated circuits Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994. :515-518 1994
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Energy consumption
Decoding
Resistors
Capacitors
Parasitic capacitance
Digital circuits
Clocks
Timing
Switches
- Language
A new successive-approximation analog-to-digital (A/D) converter is described. New interpolated C-R DAC, new R-ladder-steering decoder and constant-current comparator have been applied in the A/D converter. By adopting these techniques, high-resolution (12 bit accuracy) and high-speed conversion (1 MHz) with low power consumption (1 mW) has been realized. This chip has been fabricated by double metal and double polysilicon 0.8 /spl mu/m CMOS process, and the die size is 2.4/spl times/1.7 mm/sup 2/.ETX