A Synthesis Method for Verilog Case Statement Using Mux-and-Inverter Graph
- Resource Type
- Conference
- Authors
- Wang, Zhuoli; Chen, Lei; Wang, Shuo; Zhou, Jing; Tian, Chunsheng; Feng, Hanxu
- Source
- 2023 International Symposium of Electronics Design Automation (ISEDA) Electronics Design Automation (ISEDA), 2023 International Symposium of. :174-178 May, 2023
- Subject
- Components, Circuits, Devices and Systems
Computing and Processing
Engineering Profession
General Topics for Engineers
Photonics and Electrooptics
Electric potential
Computer aided software engineering
Design automation
Delays
Hardware design languages
Optimization
Multiprocessing systems
case statement
logic synthesis
Binary decision diagram
And-inverter graph
- Language
Crossbar architectures are widely used in high-performance network switches, such as connecting PEs in multiprocessor systems. The crossbar is usually synthesized by CASE statements in Verilog, and its delay largely affects the performance of the whole design. We proposed a multi-strategy synthesis method exclusively for CASE statements. Based on mux-and-inverter graph (MAIG), this method simplifies selection logic using the Boolean characteristic. Experimental result shows that this method could bring 4.30% less area and 16.3% less delay than Yosys.