The choice of the package for switching power regulators has a considerable impact both on the performances and final cost of the products. Thus, the current market trend is to adopt cheaper packages, like small SOT, even in complex devices as DC-DC regulators. However, due to their limited number of pins, single leads have to share paths for both signal and power domains. In this way, the fluctuations on power voltages generated on package parasites by the switching activities, are transferred to the analog signal blocks of the device. This may trigger unexpected behaviors of the device, especially when increasing the current load. These undesired behaviors are not reproducible by simulation on the design phase without the adoption of an accurate model of package parasites. In this work a method to extract a SPICE model of the package electrical parasites, based on Finite Element Method (FEM) and Boundary Element Method (BEM) by using Ansys Q3D Extractor is illustrated. This model has been integrated in the silicon design simulation environment to correctly evaluate the performances in noisy conditions of a silicon demonstrator. The comparison between simulations and experimental results has been performed to confirm the reliability of this methodology.