Analysis of system bus on SoC platform using TSV interconnection
- Resource Type
- Conference
- Authors
- Kyoungrok Cho; Hyeon-Seok Na; Tae Won Cho; Younggap You
- Source
- 2012 4th Asia Symposium on Quality Electronic Design (ASQED) Quality Electronic Design (ASQED), 2012 4th Asia Symposium on. :227-231 Jul, 2012
- Subject
- Power, Energy and Industry Applications
Components, Circuits, Devices and Systems
Through-silicon vias
Throughput
System-on-a-chip
Bridge circuits
IP networks
Silicon
Clocks
Latency model
system bus
SoC
through silicon via
throughput
- Language
This paper proposes a latency model for a multi-layer system on chip (SoC) structure employing through silicon vias (TSVs). TSVs are used to interconnect multiple SoC chips stacked to form a three-dimensional (3-D) structure. The proposed latency model has been used to estimate the system performance. The performance estimation reflects the number of IPs connected to the system bus, data throughput and the number of masters in the system. The maximum throughput calculation results can be used to find the appropriate number of chips to be stacked during the 3-D multi-layer SoC system design process.