At 28nm technology and below, hot spot prediction and process window control on production wafers have become increasingly critical to prevent sensitive pattern geometries from becoming yield limiting defects as a result of process variation. We previously established a systematic approach to identify focus-sensitive hotspots, characterize their process window margins, use a focus variation map to predict patterning defect locations, and verify predictions by guided e-beam inspection [1]. The current paper establishes the impact of intra-die micro-topography and its correlation with best focus variations of hotspots in a production chip layout. For this purpose, we obtain high-resolution topography measurements from an offline tool, and determine pattern-dependent best focus shifts from litho simulations to compare against the measured best focus distribution. We exercise the entire prediction and guided verification flow for after-etch application on a production use case with full-stack topography wafers.