Design and Implementation of the PBIW Instruction Decoder in a Softcore Embedded Processor
- Resource Type
- Conference
- Authors
- Marks, Renan; Araujo, Felipe; Santos, Renato; Yonehara, Felipe; Santos, Ricardo
- Source
- 2012 13th Symposium on Computer Systems Computer Systems (WSCAD-SSC), 2012 13th Symposium on. :110-117 Oct, 2012
- Subject
- Computing and Processing
Components, Circuits, Devices and Systems
Communication, Networking and Broadcast Technologies
Decoding
Encoding
Memory management
Hardware
Field programmable gate arrays
Thumb
Educational institutions
PBIW
hardware decoder
FPGA
r-vex
instruction encoding
- Language
This paper presents the PBIW (Pattern Based Instruction Word) instruction encoding technique on the \RVEX embedded soft core processor. The PBIW encoding technique maps the assembly generated by a compiler into an encoding scheme of a target processor. The results obtained shows that the PBIW encoding has a compression ratio ranging from 60.97% to 115.91% among the evaluated programs. The impact of PBIW encoding in the memory access shows significant performance gains since there are improvements in hit ratio up to 58.93%. The PBIW decoder experiments show that the adoption of PBIW decoder circuit shrinks the processor total area in 15% (on average) and dynamic power reduction in 40%. In addition, the PBIW decoder reduces 56% and 52% the dynamic power consumption and the amount of data stored (memory bits of M4K memory blocks) in the instruction memory.